2022-08-20 / Last updated : 2023-01-29 admin Simulator Matrix Multiplication based on the RISC-V Vector Extension We have created a matrix multiplication kernel based on the RISC-V Vector Extension (RVV) and evaluated its performance using an RTL simulator.
2022-08-06 / Last updated : 2022-09-23 admin FPGA Running ONNX Model on FPGA with Gemmini SoC We have successfully run ONNX model on an FPGA board with a DNN accelerator Gemmini and a RISC-V CPU Rocket.
2022-07-16 / Last updated : 2022-12-10 admin Simulator Benchmarks on RV64GC RISC-V Out-of-Order Simulator Since the RISC-V Out-of-Order core NaxRiscv now supports RV[32|64]GC, we have created an RV64GC simulator and ran the benchmarks CoreMark, Dhrystone, and Whetstone.
2022-07-02 / Last updated : 2022-07-03 admin FPGA Building an ML Processor using CFU Playground (Part 3) We have built a machine learning (ML) processor that leverages RISC-V custom instructions to accelerate MobileNetV2 inference 5.5 times.
2022-06-18 / Last updated : 2022-10-22 admin Simulator Running Auto-Vectorized Program on RISC-V Vector RTL Simulator In order to utilize the RISC-V “V” vector extension (RVV), we have built programs using LLVM/Clang automatic vectorization and ran them on RTL simulator of Vicuna, which complies with the RVV specification v1.0.
2022-06-04 / Last updated : 2022-09-23 admin FPGA Running ResNet-50 on FPGA with Gemmini SoC We have successfully built a DNN system using the DNN accelerator Gemmini and the RISC-V CPU Rocket on a Digilent FPGA board and run ResNet-50.
2022-05-21 / Last updated : 2022-12-10 admin FPGA Running 32-bit Linux on FPGAs with RISC-V Out-of-Order Core We have successfully created gatewares for SoC of NaxRiscv, a RISC-V Out-of-Order core, for Digilent FPGA boards and run 32-bit Linux.
2022-05-07 / Last updated : 2022-08-21 admin FPGA Building an ML Processor using CFU Playground (Part 2) We have built a machine learning (ML) processor that leverages RISC-V custom instructions to accelerate Keyword Spotting model inference 8.9 times.
2022-04-16 / Last updated : 2022-04-16 admin Simulator Running CoreMark on SonicBOOM Simulator We have created a simulator with the short-forwards branch (SFB) optimization of SonicBOOM, an out-of-order execution superscalar RISC-V CPU, and ran CoreMark.
2022-04-02 / Last updated : 2022-08-06 admin Simulator Running Test Programs on Gemmini Simulators We built an environment for Chipyard, a RISC-V SoC design framework, created simulators for Gemmini, a DNN accelerator, and ran the test programs gemmini-rocc-tests.
