2023-04-22 / Last updated : 2023-04-21 admin Simulator GEMM based on the RISC-V Vector Extension (Part 3) We have created a GEMM-compatible floating-point matrix multiplication kernel based on the RISC-V Vector Extension and evaluated its performance using Ara’s RTL simulator.
2023-03-25 / Last updated : 2023-03-25 admin Simulator GEMM based on the RISC-V Vector Extension (Part 2) We have evaluated vector load/store performance using Ara’s RTL simulator for transposed matrix support of matrix multiplication kernels based on the RISC-V Vector Extension.
2023-03-11 / Last updated : 2023-03-11 admin Simulator Vortex: OpenCL Compatible RISC-V Based GPGPU (Part 2) This article introduces the OpenCL support of Vortex, a RISC-V based open source GPGPU.
2023-02-25 / Last updated : 2023-03-11 admin Simulator GEMM based on the RISC-V Vector Extension (Part 1) We created double-, single- and half-precision floating-point matrix multiplication kernels based on the RISC-V Vector Extension and evaluated their performance using Ara’s RTL simulator.
2023-01-14 / Last updated : 2023-03-11 admin Simulator Vortex: OpenCL Compatible RISC-V Based GPGPU (Part 1) This article introduces an overview of Vortex, an open source RISC-V based GPGPU, and how to run the OpenCL program using the Vortex simulator.
2022-10-22 / Last updated : 2023-01-25 admin Simulator 1×1 Convolution based on the RISC-V Vector Extension We have created a 1×1 convolution kernel based on the RISC-V Vector Extension (RVV) and evaluated its performance using an RTL simulator.
2022-08-20 / Last updated : 2023-01-29 admin Simulator Matrix Multiplication based on the RISC-V Vector Extension We have created a matrix multiplication kernel based on the RISC-V Vector Extension (RVV) and evaluated its performance using an RTL simulator.
2022-07-16 / Last updated : 2022-12-10 admin Simulator Benchmarks on RV64GC RISC-V Out-of-Order Simulator Since the RISC-V Out-of-Order core NaxRiscv now supports RV[32|64]GC, we have created an RV64GC simulator and ran the benchmarks CoreMark, Dhrystone, and Whetstone.
2022-06-18 / Last updated : 2022-10-22 admin Simulator Running Auto-Vectorized Program on RISC-V Vector RTL Simulator In order to utilize the RISC-V “V” vector extension (RVV), we have built programs using LLVM/Clang automatic vectorization and ran them on RTL simulator of Vicuna, which complies with the RVV specification v1.0.
2022-04-16 / Last updated : 2022-04-16 admin Simulator Running CoreMark on SonicBOOM Simulator We have created a simulator with the short-forwards branch (SFB) optimization of SonicBOOM, an out-of-order execution superscalar RISC-V CPU, and ran CoreMark.
