2023-01-28 / Last updated : 2023-01-27 admin FPGA TFLite Micro on RISC-V Out-of-Order Core with Custom Instructions We have accelerated inference on Google’s TensorFlow Lite for Microcontrollers by adding SIMD instructions as custom instructions to NaxRiscv, a RISC-V out-of-order core.
2022-11-19 / Last updated : 2022-12-10 admin FPGA TensorFlow Lite for Microcontrollers on RISC-V Out-of-Order Core We have successfully run Google’s TensorFlow Lite for Microcontrollers on an FPGA board implementing NaxRiscv, a RISC-V Out-of-Order core.
2022-09-24 / Last updated : 2022-12-10 admin FPGA Running Debian on FPGA with RISC-V Out-of-Order Core We have successfully built the gateware for RV64GC NaxRiscv, a RISC-V Out-of-Order core, for Digilent FPGA board and run Debian.
2022-07-16 / Last updated : 2022-12-10 admin Simulator Benchmarks on RV64GC RISC-V Out-of-Order Simulator Since the RISC-V Out-of-Order core NaxRiscv now supports RV[32|64]GC, we have created an RV64GC simulator and ran the benchmarks CoreMark, Dhrystone, and Whetstone.
2022-05-21 / Last updated : 2022-12-10 admin FPGA Running 32-bit Linux on FPGAs with RISC-V Out-of-Order Core We have successfully created gatewares for SoC of NaxRiscv, a RISC-V Out-of-Order core, for Digilent FPGA boards and run 32-bit Linux.
2022-03-19 / Last updated : 2022-12-10 admin Simulator Benchmarks on RISC-V Out-of-Order Simulator We have created a simulator for NaxRiscv, a RISC-V Out-of-Order core, and ran the benchmarks CoreMark and Dhrystone.
