2023-04-22 / Last updated : 2023-04-21 admin Simulator GEMM based on the RISC-V Vector Extension (Part 3) We have created a GEMM-compatible floating-point matrix multiplication kernel based on the RISC-V Vector Extension and evaluated its performance using Ara’s RTL simulator.
2023-03-25 / Last updated : 2023-03-25 admin Simulator GEMM based on the RISC-V Vector Extension (Part 2) We have evaluated vector load/store performance using Ara’s RTL simulator for transposed matrix support of matrix multiplication kernels based on the RISC-V Vector Extension.
2023-02-25 / Last updated : 2023-03-11 admin Simulator GEMM based on the RISC-V Vector Extension (Part 1) We created double-, single- and half-precision floating-point matrix multiplication kernels based on the RISC-V Vector Extension and evaluated their performance using Ara’s RTL simulator.
2023-02-11 / Last updated : 2023-02-10 admin FPGA OpenBLAS on 32-bit RISC-V Multi-Core We made OpenBLAS compatible with 32-bit RISC-V and evaluated the performance of GEMM using an FPGA board with octa-core 32-bit RISC-V SoC.
2023-01-28 / Last updated : 2023-01-27 admin FPGA TFLite Micro on RISC-V Out-of-Order Core with Custom Instructions We have accelerated inference on Google’s TensorFlow Lite for Microcontrollers by adding SIMD instructions as custom instructions to NaxRiscv, a RISC-V out-of-order core.
2022-12-24 / Last updated : 2023-01-25 admin FPGA Matrix Multiplication on FPGA with the RISC-V Vector Extension We have implemented Vicuna, an implementation of the RISC-V Vector Extension, on an FPGA board and evaluated the performance of the matrix multiplication kernel.
2022-12-10 / Last updated : 2023-01-25 admin FPGA OpenMP on FPGA with RISC-V Multi-Core Processor We have implemented a RISC-V multi-core processor on an FPGA board and evaluated the performance of the matrix multiplication kernel using OpenMP.
2022-11-19 / Last updated : 2022-12-10 admin FPGA TensorFlow Lite for Microcontrollers on RISC-V Out-of-Order Core We have successfully run Google’s TensorFlow Lite for Microcontrollers on an FPGA board implementing NaxRiscv, a RISC-V Out-of-Order core.
2022-09-24 / Last updated : 2022-12-10 admin FPGA Running Debian on FPGA with RISC-V Out-of-Order Core We have successfully built the gateware for RV64GC NaxRiscv, a RISC-V Out-of-Order core, for Digilent FPGA board and run Debian.
2022-07-16 / Last updated : 2022-12-10 admin Simulator Benchmarks on RV64GC RISC-V Out-of-Order Simulator Since the RISC-V Out-of-Order core NaxRiscv now supports RV[32|64]GC, we have created an RV64GC simulator and ran the benchmarks CoreMark, Dhrystone, and Whetstone.
