2023-01-28 / Last updated : 2023-01-27 admin FPGA TFLite Micro on RISC-V Out-of-Order Core with Custom Instructions We have accelerated inference on Google’s TensorFlow Lite for Microcontrollers by adding SIMD instructions as custom instructions to NaxRiscv, a RISC-V out-of-order core.
2022-11-19 / Last updated : 2022-12-10 admin FPGA TensorFlow Lite for Microcontrollers on RISC-V Out-of-Order Core We have successfully run Google’s TensorFlow Lite for Microcontrollers on an FPGA board implementing NaxRiscv, a RISC-V Out-of-Order core.
2022-11-05 / Last updated : 2022-11-04 admin FPGA Applying the Tiny Matrix Extension to ML Inference We have accelerated machine learning (ML) model inference using a RISC-V processor that accelerates matrix multiplication at low resource cost.
2022-10-22 / Last updated : 2023-01-25 admin Simulator 1×1 Convolution based on the RISC-V Vector Extension We have created a 1×1 convolution kernel based on the RISC-V Vector Extension (RVV) and evaluated its performance using an RTL simulator.
2022-09-10 / Last updated : 2023-01-25 admin FPGA Tiny Matrix Extension using RISC-V Custom Instructions We have developed a processor that accelerates matrix multiplication using RISC-V custom instructions, implemented it on an FPGA board, and evaluated its performance.
2022-08-20 / Last updated : 2023-01-29 admin Simulator Matrix Multiplication based on the RISC-V Vector Extension We have created a matrix multiplication kernel based on the RISC-V Vector Extension (RVV) and evaluated its performance using an RTL simulator.
2022-08-06 / Last updated : 2022-09-23 admin FPGA Running ONNX Model on FPGA with Gemmini SoC We have successfully run ONNX model on an FPGA board with a DNN accelerator Gemmini and a RISC-V CPU Rocket.
2022-07-02 / Last updated : 2022-07-03 admin FPGA Building an ML Processor using CFU Playground (Part 3) We have built a machine learning (ML) processor that leverages RISC-V custom instructions to accelerate MobileNetV2 inference 5.5 times.
2022-06-04 / Last updated : 2022-09-23 admin FPGA Running ResNet-50 on FPGA with Gemmini SoC We have successfully built a DNN system using the DNN accelerator Gemmini and the RISC-V CPU Rocket on a Digilent FPGA board and run ResNet-50.
2022-05-07 / Last updated : 2022-08-21 admin FPGA Building an ML Processor using CFU Playground (Part 2) We have built a machine learning (ML) processor that leverages RISC-V custom instructions to accelerate Keyword Spotting model inference 8.9 times.
