2022-11-19 / Last updated : 2022-12-10 admin FPGA TensorFlow Lite for Microcontrollers on RISC-V Out-of-Order Core We have successfully run Google’s TensorFlow Lite for Microcontrollers on an FPGA board implementing NaxRiscv, a RISC-V Out-of-Order core.
2022-11-05 / Last updated : 2022-11-04 admin FPGA Applying the Tiny Matrix Extension to ML Inference We have accelerated machine learning (ML) model inference using a RISC-V processor that accelerates matrix multiplication at low resource cost.
2022-10-22 / Last updated : 2023-01-25 admin Simulator 1×1 Convolution based on the RISC-V Vector Extension We have created a 1×1 convolution kernel based on the RISC-V Vector Extension (RVV) and evaluated its performance using an RTL simulator.
2022-10-08 / Last updated : 2022-12-09 admin FPGA Running Dual-Core RISC-V Linux on Cheap FPGA Board We have successfully built a dual-core 32-bit RISC-V SoC for a Sipeed Tang Primer that we purchased for about $20 and run Linux.
2022-09-24 / Last updated : 2022-12-10 admin FPGA Running Debian on FPGA with RISC-V Out-of-Order Core We have successfully built the gateware for RV64GC NaxRiscv, a RISC-V Out-of-Order core, for Digilent FPGA board and run Debian.
2022-09-10 / Last updated : 2023-01-25 admin FPGA Tiny Matrix Extension using RISC-V Custom Instructions We have developed a processor that accelerates matrix multiplication using RISC-V custom instructions, implemented it on an FPGA board, and evaluated its performance.
2022-08-20 / Last updated : 2023-01-29 admin Simulator Matrix Multiplication based on the RISC-V Vector Extension We have created a matrix multiplication kernel based on the RISC-V Vector Extension (RVV) and evaluated its performance using an RTL simulator.
2022-08-06 / Last updated : 2022-09-23 admin FPGA Running ONNX Model on FPGA with Gemmini SoC We have successfully run ONNX model on an FPGA board with a DNN accelerator Gemmini and a RISC-V CPU Rocket.
2022-07-16 / Last updated : 2022-12-10 admin Simulator Benchmarks on RV64GC RISC-V Out-of-Order Simulator Since the RISC-V Out-of-Order core NaxRiscv now supports RV[32|64]GC, we have created an RV64GC simulator and ran the benchmarks CoreMark, Dhrystone, and Whetstone.
2022-07-02 / Last updated : 2022-07-03 admin FPGA Building an ML Processor using CFU Playground (Part 3) We have built a machine learning (ML) processor that leverages RISC-V custom instructions to accelerate MobileNetV2 inference 5.5 times.
