2023-04-22 / Last updated : 2023-04-21 admin Simulator GEMM based on the RISC-V Vector Extension (Part 3) We have created a GEMM-compatible floating-point matrix multiplication kernel based on the RISC-V Vector Extension and evaluated its performance using Ara’s RTL simulator.
2023-03-25 / Last updated : 2023-03-25 admin Simulator GEMM based on the RISC-V Vector Extension (Part 2) We have evaluated vector load/store performance using Ara’s RTL simulator for transposed matrix support of matrix multiplication kernels based on the RISC-V Vector Extension.
2023-02-25 / Last updated : 2023-03-11 admin Simulator GEMM based on the RISC-V Vector Extension (Part 1) We created double-, single- and half-precision floating-point matrix multiplication kernels based on the RISC-V Vector Extension and evaluated their performance using Ara’s RTL simulator.
2022-12-24 / Last updated : 2023-01-25 admin FPGA Matrix Multiplication on FPGA with the RISC-V Vector Extension We have implemented Vicuna, an implementation of the RISC-V Vector Extension, on an FPGA board and evaluated the performance of the matrix multiplication kernel.
2022-10-22 / Last updated : 2023-01-25 admin Simulator 1×1 Convolution based on the RISC-V Vector Extension We have created a 1×1 convolution kernel based on the RISC-V Vector Extension (RVV) and evaluated its performance using an RTL simulator.
2022-08-20 / Last updated : 2023-01-29 admin Simulator Matrix Multiplication based on the RISC-V Vector Extension We have created a matrix multiplication kernel based on the RISC-V Vector Extension (RVV) and evaluated its performance using an RTL simulator.
2022-06-18 / Last updated : 2022-10-22 admin Simulator Running Auto-Vectorized Program on RISC-V Vector RTL Simulator In order to utilize the RISC-V “V” vector extension (RVV), we have built programs using LLVM/Clang automatic vectorization and ran them on RTL simulator of Vicuna, which complies with the RVV specification v1.0.
