2023-01-28 / Last updated : 2023-01-27 admin FPGA TFLite Micro on RISC-V Out-of-Order Core with Custom Instructions We have accelerated inference on Google’s TensorFlow Lite for Microcontrollers by adding SIMD instructions as custom instructions to NaxRiscv, a RISC-V out-of-order core.
2022-11-19 / Last updated : 2022-12-10 admin FPGA TensorFlow Lite for Microcontrollers on RISC-V Out-of-Order Core We have successfully run Google’s TensorFlow Lite for Microcontrollers on an FPGA board implementing NaxRiscv, a RISC-V Out-of-Order core.
2022-11-05 / Last updated : 2022-11-04 admin FPGA Applying the Tiny Matrix Extension to ML Inference We have accelerated machine learning (ML) model inference using a RISC-V processor that accelerates matrix multiplication at low resource cost.
2022-07-02 / Last updated : 2022-07-03 admin FPGA Building an ML Processor using CFU Playground (Part 3) We have built a machine learning (ML) processor that leverages RISC-V custom instructions to accelerate MobileNetV2 inference 5.5 times.
2022-05-07 / Last updated : 2022-08-21 admin FPGA Building an ML Processor using CFU Playground (Part 2) We have built a machine learning (ML) processor that leverages RISC-V custom instructions to accelerate Keyword Spotting model inference 8.9 times.
2022-03-05 / Last updated : 2022-08-21 admin FPGA Building an ML Processor using CFU Playground (Part 1) We have built a machine learning (ML) processor that leverages RISC-V custom instructions to accelerate Person Detection int8 model inference 5.6 times.
